module top(
    input   clk,
    input   rst_n,
    
    output        debug_wb_have_inst,
    output [31:0] debug_wb_pc,
    output        debug_wb_ena,
    output [4:0]  debug_wb_reg,
    output [31:0] debug_wb_value

    );
    
    wire [31:0] inst, pc;
    wire [31:0] rd, adr, wdin;
    wire we;
    
    debug_CPU debug_CPU_U(
        .clk            (clk),
        .rst_n          (rst_n),
        
        .irom_inst      (inst),     // input
        .irom_pc        (pc),       // output
        
        .dram_rd        (rd),       // input
        .dram_adr       (adr),      // output
        .dram_wdin      (wdin),     // output 
        .dram_we        (we),       // output
        
        .debug_wb_have_inst (debug_wb_have_inst),
        .debug_wb_pc        (debug_wb_pc),
        .debug_wb_ena       (debug_wb_ena),
        .debug_wb_reg       (debug_wb_reg),
        .debug_wb_value     (debug_wb_value)
    );
    
    assign ram_clk = !clk;
    
    
   inst_mem imem(
       .a          (pc[15:2]),
       .spo        (inst)
   );

   data_mem dmem(
       .clk    (ram_clk),
       .a      (adr[15:2]),
       .spo    (rd),
       .we     (we),
       .d      (wdin)
   );

endmodule
